10GBase-R PCS (IEEE 802.3 Clause 49)
$0.00
156.25 & 312.5Mhz clock rates in V7 or Ultrascale FPGAs
Low resource count
Interoperable with Xilinx PMA (SERDES)
Allows easy migration between FPGA families or ASICs (Vendor agnostic code)
156.25 & 312.5Mhz clock rates in V7 or Ultrascale FPGAs
Low resource count
Interoperable with Xilinx PMA (SERDES)
Allows easy migration between FPGA families or ASICs (Vendor agnostic code)
156.25 & 312.5Mhz clock rates in V7 or Ultrascale FPGAs
Low resource count
Interoperable with Xilinx PMA (SERDES)
Allows easy migration between FPGA families or ASICs (Vendor agnostic code)
